1. Field of the Invention
The present invention relates to a method of forming a semiconductor device structure. More particularly, the present invention relates to a method of forming a buried doped region underneath an isolation layer.
2. Description of the Related Art
Among the types of semiconductor devices, metal-oxide-semiconductor (MOS) is one of most important and widely used semiconductor devices because of its low power consumption and suitability for high density integration.
In general, the gate and the source/drain regions of a MOS device are fabricated on the surface of a substrate. The gate is disposed on the surface of a wafer and the source/drain regions are disposed on the two sides of the gate. The channel region underneath the gate and between the source/drain regions is formed in parallel to the surface of the substrate, the so-called horizontal channel structure. However, with the increase in the level of integration of the semiconductor devices, the size of each MOS device is reduced. As the MOS device is miniaturized, the channel length is reduced and the operating speed of the semiconductor device is increased. Yet, the length of the channel cannot be reduced without limit. When the channel length is reduced to a critical level, abnormal punch through between the source and the drain will occur with higher frequency and the so-called short channel effect such as the hot electron effect will intensify so that the electrical performance of the device can be seriously affected.
On the other hand, the channel length of the aforementioned horizontal type device is mainly determined by the length of the gate and the gate is fabricated by performing photolithographic and etching process. Since any photolithographic process has the so-called critical dimension (CD) problem, the gate line width will encounter a barrier to further reduction and hence the miniaturization of the semiconductor devices.
As a result, the semiconductor industry has developed a trench semiconductor manufacturing technique, in which the MOS device is fabricated within the trenches. For example, the source/drain regions are formed on the top and the bottom of the trench and the gate is formed within the trench. The channel region between the source/drain regions is set up in a direction perpendicular to the surface of the substrate to form the so-called vertical channel device. Because the channel length in the trench type semiconductor device is dependent upon the depth of the trench, critical dimension (CD) problem related to a photolithographic process can be avoided. Hence, the dimension of each device can be minimized and their area occupation on the wafer can be reduced. In other words, the level of integration of the semiconductor devices can be increased.
However, in the aforementioned trench-type semiconductor device, one of the source/drain regions (the doped region) is disposed at the bottom of the trench. Typically, the source/drain region (the doped region) is formed at the bottom of the device isolation structure or the bottom of the trench in an ion implant process after forming the device isolation structure (for example, a shallow trench isolation (STI) structure). Because dopants need to penetrate the device isolation structure (the shallow trench isolation (STI) structure) in the ion implant process, the implant depth of the dopants is increased. With a larger implant depth, not only is the process of implanting dopants to an appropriate depth more difficult but a larger amount of the energy is also needed to accelerate the ions to the required level for the ion implant process. Ultimately, the ion implant process is more difficult to control and a higher production cost is incurred.